1. Field of Invention
The present invention relates to a power stage control circuit; particularly, it relates to a power stage control circuit with feedback terminal short-circuit protection.
2. Description of Related Art
FIG. 1 shows a schematic diagram of a prior art power stage control circuit. As shown in FIG. 1, a power stage 10 converts an input voltage Vin to an output voltage Vout (or to an output current, depending on whether a load circuit requires a stable voltage or a stable current). The output terminal is connected to ground through two resistors Z1 and Z2 connected in series. The resistor Z2 is coupled between a feedback terminal FB of a power stage control circuit 20 and ground. The voltage across the resistor Z2 is the feedback voltage Vfb which is inputted to one input terminal of an error amplifier circuit 22 in the power stage control circuit 20. The error amplifier circuit 22 compares the feedback voltage Vfb with a reference signal Vref, and generates an error amplified signal which is inputted to a driver circuit 21. The driver circuit 21 generates a driver signal according to the error amplified signal, to drive the power stage 10.
When the feedback terminal FB is shorted to ground, the error amplifier circuit 22 will generate an abnormal comparison output, and in response, the driver circuit 21 will generate an abnormal driver signal which will keep driving the power stage 10 to increase the output voltage. This will result in damages to the circuit. To avoid this, the prior art power control circuit 20 includes a comparator circuit 23, whose one input terminal receives the feedback voltage Vfb, and the other input terminal receives a short-circuit threshold voltage Vfbs (for example, the short-circuit threshold voltage Vfbs may be 0.15V). The comparator circuit 23 compares the feedback voltage Vfb with the short-circuit threshold voltage Vfbs; when the feedback voltage Vfb is smaller than the short-circuit threshold voltage Vfbs, it is determined that a short-circuit condition occurs at the feedback terminal FB, and a fault signal is generated to stop the operation of the power stage 10.
However, in the initial stage when the circuit begins to operate, since the power stage 10 has not yet or just started to operate, the output voltage Vout is zero or extremely low. Therefore, the comparison by the comparator circuit 23 in the initial stage is inaccurate and will induce misjudgment of the short-circuit condition at the feedback terminal FB. To avoid such misjudgment, the output of the comparator circuit 23 should be masked during the initial stage. Typically, in the initial stage, a power ON reset (POR) circuit 25 will output a POR signal which is sent to the driver circuit 21 to start a power ON procedure. Thus, a blanking circuit 24 can be provided which is triggered by the POR signal to generate a blanking signal inv_BL, and blanking signal inv_BL is sent to an AND logic gate 26 to mask the output of the comparator circuit 23 as shown in FIG. 1.
FIG. 2A shows the signal waveforms of the circuit shown in FIG. 1 during a normal power ON procedure. When the POR signal is at high level, the power ON procedure starts. Let us assume that the regulation target of the output voltage Vout is Vout_set and its corresponding feedback voltage Vfb is 1.25V, i.e., the reference signal Vref is set to 1.25V, and the short-circuit threshold voltage Vfbs for example may be set to 0.15V. To avoid the misjudgment in the initial stage, the blanking circuit 24 generates the blanking signal inv_BL which delays a blanking period Tbk to ensure that the feedback voltage Vfb has crossed over the predetermined short-circuit threshold voltage Vfbs as it gradually increases from the ground voltage during the initial stage. Only after the blanking signal inv_LB is at high level, the comparison result of the comparator circuit 23 is allowed to pass through the AND logic gate 26 to the driver circuit 21, as an accurate fault signal FAULT.
However, in different applications, the input voltage Vin, the output voltage Vout, and the load condition may be different. This will result in different rising speed of the feedback voltage Vfb, and therefore the blanking period Tbk (i.e. the setting of the blanking signal inv_BL) must be long enough to avoid misjudgment even at minimum input voltage Vin and maximum loading. However, as shown in FIG. 2B, if the input voltage Vin is high and there is no load, short-circuit may occur at the feedback terminal FB before the short-circuit protection mechanism starts to function, causing damages to the circuit. Therefore, it is not a good approach in the prior art power stage control circuit to temporarily disable the short-circuit protection for the feedback terminal FB within the blanking period Tbk during circuit initial stage.
In view of the foregoing, the present invention provides a power stage control circuit with feedback terminal short-circuit protection which does not require setting the blanking period Tbk, such that the short-circuit protection for the feedback terminal does not need to be disabled in the circuit initial stage.